As an RFIC-PLL Designer, you will provide analog and digital PLL solutions for wireless SoC and drive them to mass production for Apple’s Wireless Connectivity products. Responsibilities include: - Lead design of radio transceiver chains including analog PLLs - VCOs, digital PLLs - DCOs, LOGen, and chain of blocks in RX and TX. - Drive radio KPI (power, area, performance) to meet product requirements. Work with multi-functional teams, including platform architecture, wireless design, RF HW, and SW, to define radio features enabling wireless innovation. - Work closely with RF Systems on block-level and high-level specifications of the PLL-LOGen, TX, and RX line-ups and the accurate distribution of spec margins in the chain. - Hands-on design contributions, from concept, architecture, and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations, and extractions. - Responsible for the floorplan layout and verification of the design to ensure a successful tape-out and work through Co-Existence scenarios and design to meet the CoEx requirements. - Provide design versus silicon measurements correlation and compliance with volume production specifications.